Flash EEPROM devices typically include a semiconductor substrate of first conductivity type (e.g., P-type), spaced source and drain regions of second conductivity (e.g., N-type) in the substrate, a channel region at a face of the substrate, between the spaced source and drain regions, a floating gate for storing charge carriers when the device is programmed and a control gate which overlies the floating gate, opposite the channel region.
Operations of such flash EEPROM devices are typically classified into three modes, i.e., programming, erasing and reading.
Regular programming of a flash EEPROM is typically achieved by biasing the drain region of a selected memory cell transistor to a first positive bias (e.g., 5-6 V) relative to the source region thereof, and biasing the control gate thereof to a second positive bias (e.g., 8-12 V) which is greater than the first positive bias. In the absence of any stored charge on the floating gate, these biases cause the formation of an inversion-layer channel of electrons at the face of the substrate, between the source and drain regions. As will be understood by those skilled in the art, the drain-to-source voltage accelerates these electrons through the channel to the drain region where they acquire sufficiently large kinetic energy and are typically referred to as "hot" electrons. The larger positive bias on the control gate also establishes an electrical field in a tunneling oxide layer which separates the floating gate from the channel region. This electric field attracts the hot electrons and accelerates them toward the floating gate, which is disposed between the control gate and the channel region, by a process known as tunneling. The floating gate then traps the hot electrons and accumulates them. Fortunately, the process of charging the floating gate is self-limiting. The negative charge accumulates on the floating gate, which in turn reduces the strength of the electric field in the tunneling oxide layer to the point where it is no longer capable of accelerating "hot" electrons from the drain side of the channel region. As will be understood by those skilled in the art, the accumulation of a large quantity of trapped electrons on the floating gate will cause the effective threshold voltage V.sub.th of the field effect transistor to increase (e.g., up to about 6-7 V). If this increase is sufficiently large, the field effect transistor will remain in a nonconductive "off" state when a predetermine "read" voltage V.sub.read (e.g., 4-5 V) is applied to the control gate during a regular reading operation because V.sub.th is greater than V.sub.read. In this state, known as the programmed state, the EEPROM cell May be said to be storing a logic "0", or be called an "off-cell". Once programmed the EEPROM cell remains in its higher threshold voltage even when it power supply is interrupted or tuned off for long periods of time.
Erasing the EEPROM cell is to remove the charge accumulated in its floating gate. The erase operation of the cell can be carried out, for example, by applying a negative bias (e.g., about -10 V) to its control gate, and a third positive bias (e.g., 5-6 V) to its bulk, having its source and drain floated. This causes cold electron tunneling (i.e., Fowler-Nordheim tunneling) through the thin insulation (e.g., below 100 A) between the floating gate and the bulk, leading to a decrease in the threshold voltage of the EEPROM cell (e.g., 1-3 V). The erase voltages may be applied to the cell until it is erased below a maximum threshold voltage acceptable. Accordingly, if a flash cell has been erased, it will conduct heavily. In this case, the cell may be said to be storing a logic "1", or be called an "on-cell". Thus, by monitoring the bit line current, the programmed or erased state (i.e., 1 or 0) of the cell can be determined.
Regular reading of the EEPROM cell is achieved by applying the read voltage V.sub.read to the control gate, typically via a word line connecting a row of identical EEPROM cells, and applying a fourth positive bias (about 1 V) to the drain region, typically via a bit line connecting a column of identical EEPROM cells. If the EEPROM cell is programmed, it will not conduct drain current I.sub.dc. If, however, the EEPROM cell has not been programmed (or has been erased), it will conduct heavily. By monitoring the bit line current, thus, the programmed state (i.e., 1 or 0) of the EEPROM cell can be determined.
Because of their advance performance characteristics, including higher programming speeds and lower power consumption, high density flash memories have recently proven useful as mass storage devices (or storage media) for portable electronic devices (such as digital still cameras and memory cards) and hard disks in personal computers, among other things.
Industry desires for more efficient integration density in a flash memory and for expanded memory capacity have led to the development of multi-bit (also known as multi-level, multi-state, or multiple bit) technology, wherein a plurality of bits are stored within a single memory cell. By providing for the storage of multiple bits within each memory cell, multi-bit technology contributes to a reduction in the cost-per-bit of data storage in flash memories that employ this technology. One prior art multi-bit configuration is disclosed on pp. 132-133 of the ISSCC Digest of Technical Papers dated Feb. 1995, in an article entitled "A Multilevel-Cell 32Mb Flash Memory", written by M. Bauer, et al. Specifically, this article discloses a cell array arranged in the NOR-type, in which a memory cell uses two bits to store one of four data states, i.e., "00", "01", "10", and "11". (As well-known to those skilled in the art, flash memories are classified into two types, namely, a "NAND-type" and a "NOR-type", in accordance with the logical configuration of the memory cells within the memory.) Each of these four states corresponds to a unique voltage level, e.g., "00"=2.5V, "01"=1.5V, "10"=0.5V, and "11"=-3V. These voltage levels are threshold values assigned to allow data to be read from memory cell having one of these four states of data stored therein. Significantly, the memory cell contains a distribution profiled corresponding to these various threshold values. Furthermore, memory cells coupled to a single word line can have threshold voltages that differ from each other.
To detect the data state of multi-bit memory cell, a read voltage having a voltage level between two threshold voltage levels, or on a lower or higher side of a threshold voltage, must be applied to a gate of each of the memory cells through a word line coupled thereto. Unfortunately, the width between adjacent threshold voltages (hereinafter referred to as a "window") is less than that found in a regular single-bit flash memory. For example, the window in a four-state flash memory is about 0.6V. Furthermore, when a word line voltage for performing a reading operation is located in a window of about 0.6V, the margin between an edge of the threshold voltage profiled and the level of the word line voltage may not be more than approximately 0.3V (as opposed to about a 1.3V margin in a regular single-bit memory). Therefore, when multi-bit flash memories are made using a manufacturing process subject to variations, or when they are influenced by variations in word line voltage level and temperature, the probability of having invalid sensing operations becomes significant.
This weak immunity against variations in external conditions suggests that the utility of the multi-bit flash memories as a storage device is limited to the storage of mass information, such as audio data, for example, where the failure to store even several data bits does not significantly disturb the organization of the information as a whole. Until now, therefore, regular single-bit flash memories have been used for storing information where reliability and stability of data storage are important, such as in the Basic Input/Output System (BIOS) or for font storage.
Recently, the present applicant has proposed a new flash memory which is disclosed in a prior U.S. patent application Ser. No. 09/010,430 entitled "NON-VOLATILE SEMICONDUCTOR MEMORY PERFORMING SINGLE-BIT AND MULTI-BIT OPERATIONS", filed Jan. 21, 1998, and issued as U.S. Pat. No. 5,982,663. Briefly, according to the disclosed flash memory, a cell array region is classified into two portions: a main memory area containing a multiplicity of memory fields, and a device data storage area containing a multiplicity of redundant fields respectively corresponding to the memory fields. In the conventional flash memory, multi-bit operations are carried out with respect to the memory fields, while single-bit operations are performed with respect to the redundant fields. Such a flash memory cell array architecture and its peripheral components are illustrated in FIG. 1.
Referring to FIG. 1, the flash memory is provided with a memory cell array 100 which includes multiple memory fields 102 for storing normal data, and multiple redundant fields 104 for storing device data such as the addresses of bad portions of normal memory cell arrays and the status of address mapping. Because the data stored in the redundant field 104 is extremely important for determining whether an access operation of the memory data is either valid or invalid, the redundant field 104 should be located in a stable single-bit retention environment, rather than in an unstable multi-bit retention area, in order to guarantee data stability.
The flash memory also comprises row and column decoders 200 and 400 which select appropriate word lines and bit lines of the memory cell array 100, using row address signals X-ADD and column address signals Y-ADD, respectively. A page buffer circuit 300 is provided to program and read data to and from the memory cell array 100. A control logic 500 is further provided for the flash memory. The control logic 500 supplies several control signals of the page buffer circuit 300 depending on externally applied commands, so as to control operation modes of the page buffer circuit 300.
FIG. 2 shows a conventional architecture of the redundant field 104, and of an associated page buffer circuit 300a. Referring to FIG. 2, each redundant field 104 comprises a plurality of strings 110. Each of the strings 110 is organized having two string selection transistors, ST1 and ST2, and a plurality of memory cells M1 through Mm. Each string is further coupled to a corresponding one of the bit lines BL1 to BLn.
In the page buffer circuit 300a, a bit line BL1 is connected to a node 340 through an NMOS depletion transistor 304 and an NMOS transistor 342. Another bit line BL2 is connected to a node 362 through an NMOS depletion transistor 304a and an NMOS transistor 364. Gates of both the NMOS depletion transistors 304 and 304a are coupled in common to a bit line shielding signal BLSHF. A gate of the NMOS transistor 342 is coupled to a column address signal Ai. Additionally, an NMOS transistor 306 has a gate coupled to a first inhibition signal IHT1, and is connected between a power source voltage Vcc and a node 302. This node 302 is located between the transistors 342 and 304. Between the power source voltage Vcc and a node 302a, another NMOS transistor 306a is connected. The transistor 306a has its gate coupled to a second inhibition signal IHT2. The node 302a is interposed between the transistors 364 and 304a.
Another NMOS transistor 350, having a gate coupled to a bit line discharge signal DCB, is connected between the node 340 and the ground Vss. Similarly, an NMOS transistor 372 has a gate coupled to the bit line discharge signal DCB, and is connected between the node 362 and the ground Vss. Constant current is supplied to the node 340 from the power source voltage through a first independent current source 344. Constant current is also supplied to the node 362 from the power source voltage through a second independent current source 366.
The node 340 is connected to a first terminal Q1 of a first data latch 354 through an NMOS transistor 348, whose gate is coupled to a first programming signal PGM1. The terminal Q1 is also connected to a first input/output line IO1. A complementary first terminal Q1 is connected to the ground Vss through NMOS transistors 356, 358 and 360, respectively. A gate of the transistor 356 is coupled to the address signal Ai, while a gate of the transistor 358 is connected to the node 340, and a gate of the transistor 360 is coupled to a latch signal LATCH. The node 362 is connected to a second terminal Q2 of a second data latch 376 through an NMOS transistor 370 whose gate is coupled to a second programming signal PGM2. The second terminal Q2 is also connected to a second input/output line IO2. A complementary second terminal Q2 is connected to the ground Vss through NMOS transistors 378, 380, and 382, respectively. A gate of the transistor 378 is coupled of another column address signal Bi, while a gate of the transistor 380 is connected to the node 362, and a gate of the transistor 382 is coupled to the latch signal LATCH. The latch signal LATCH is provided to activate the data latches 354 and 376, respectively, and is generated by a NOR gate 390 of a latch control circuit 384.
The latch control circuit 384 is supplied with several control signals RD3, EVF, PGVF2 and PGVF3 from control logic 500 of FIG. 1. The control signals RD3, EVF, PGVF2 and PGVF3 are applied as separate inputs to another NOR gate 386. An output of the NOR gate 386 is applied as a first input to the NOR gate 390, while an inverse of the read verification signal LRDVF is applied to the NOR gate 390 as a second input. FIG. 3 is a timing diagram for a reading operation of the redundant field 104 shown in FIG. 2. With reference to FIG. 3, the redundant field 104 has a read step which is performed using the same timing as the multi-bit reading sequence for the normal memory cell array in the memory field 102. As well known to one skilled in the art, a typical multi-bit (i.e., four-bit) reading sequence for the normal memory cell array includes three cycles T1, T2, and T3, as shown in FIG. 3.
For a single-bit reading operation of the redundant field 104, three read voltages 2V, 1V and 0V are sequentially applied to a selected word line in order, like the multi-bit reading operation for the memory field 102. The read signal RD3, applied to the latch control circuit 384, substantially determines when the single-bit reading operation for the redundant field 104 will be conducted. In the conventional flash memory, the single-bit reading operation for the redundant field 104 is carried out only during the third cycle T3 of the multi-bit reading operation timing under the control of the read signal RD3. However, since the conventional flash memory uses the same timing for the single-bit operation as for the multi-bit operation, the single-bit reading time accordingly increases in proportion with increase of the data states (data bits) defined for a multi-bit operation.
Based on the above, it can be appreciated that there presently exist needs in the art for flash memory devices and for methods of reading device data stored therein which overcome the above-described disadvantages and shortcomings of the presently available devices and methods.